The present invention relates to a semiconductor nonvolatile memory device and an information processing system employing such a memory device, to an effective technique for, for example, a batch erasable type EEPROM (electrically erasable and programmable read only memory), and also to a microcomputer system employing such an EEPROM.
As a semiconductor nonvolatile memory device, there are known an erasable programmable read-only memory (referred to as an xe2x80x9cEPROMxe2x80x9d) the stored information on which is erasable by utilizing ultraviolet radiation, and also an electrically erasable and programmable read-only memory (referred to as an xe2x80x9cEEPROMxe2x80x9d) the stored information of which is electrically erasable. An EPROM is suitable for a large-scale memory capacity because areas of memory cells for storing information are relatively small. However, to erase the information stored in EPROM, it is necessary to irradiate ultraviolet rays to the memory cells. To this end, a package having an ultraviolet irradiating window, which is relatively expensive, would be required in order to be able to employ such type of memory cells. Moreover, in order to be able to write or rewrite new information by a programmer, the EPROM must be removed, during write/rewrite operations thereof, from the system to which this EPROM has been actually packaged in, thereby resulting in a problem.
On the other hand, with respect to an EEPROM, the information stored therein is electrically erasable and writable, while the EEPROM remains packaged in a system. However, areas associated with memory cells of the EEPROM type are relatively large. For instance, a typical area of a memory cell in an EEPROM is 1.5 to 2 times, or as much as approximately 2.5 to 5 times, larger than that of an EPROM. Such an EEPROM is described, for example, in xe2x80x9cElectronic Technologyxe2x80x94June 1988xe2x80x9d, pages 122-127, issued by K.K. Nikkan Kogyo Shimbun, in which a detailed description is made of a construction of an EEPROM cell of a floating-gate tunnel oxide (FLOTOX), a mechanism of injection of electrons into a floating gate and of release of electrons from the floating gate, and the like.
The EEPROM cell of the FLOTOX type is a memory cell having a two-layer construction provided with a floating gate for holding electrons in the lower layer of a control gate. This mechanism is designed so that a tunnel current called a Fowlor-Nordheim (F-N) is allowed to flow through a region (a tunnel region) of an extremely thin insulating film formed in a portion of an insulating film between the floating gate and a drain region to effect injection of electrons into the floating gate and release of electrons from the floating gate.
In the memory cell of EEPROM of the FLOTOX type, electrons held by the floating gate are released, for example, by applying a GND voltage (0 V) to the control gate and applying a high voltage of 15 V to 20 V to the drain electrode.
As a result of this relatively large size of the memory cells, in general, EEPROM is not suitable when emphasis is in having a large memory capacity.
Semiconductor nonvolatile memory devices that can be considered as being between or intermediate the EPROM and EEPROM, are so-called xe2x80x9celectrically batch erasable type EEPROMxe2x80x9d devices, or are flash EEPROM devices, which have very recently been developed. These devices are the semiconductor nonvolatile memory devices in which either all of the memory cells formed in a chip, or a certain memory cell group among the memory cells formed in the chip, are electrically erased. In accordance with the electrically batch erasable type of EEPROM, or the flash EEPROM, the size of memory cells thereof can be formed to be substantially the same as that of EPROM.
Such an electrically batch erasable type EEPROM is described in, for instance, IEEE INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE in 1980, on pages 152 to 153; IEEE INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE in 1987, on pages 76 to 77; and IEEE, J. SOLID-STATE CIRCUITS, vol. 23 (1988), pages 1157 to 1163.
In FIG. 16, there is represented a schematic sectional view of the electrically batch erasable EEPROM, which has been disclosed in the International Electron Device Meeting held in 1987. The memory cell shown in FIG. 16 is very similar to the memory cell of the normal EPROM. That is to say, this memory cell is constructed in accordance with an insulated gate type field-effect transistor (simply referred to as a xe2x80x9cMOSFETxe2x80x9d or xe2x80x9ctransistorxe2x80x9d), however, having a double layer gate structure. In the structure of FIG. 16, reference numeral 8 indicates a P type silicon substrate; reference numeral 11 denotes a P type diffusion layer formed on the silicon substrate 8; reference numeral 10 represents an N type diffusion layer having a low concentration formed on the silicon substrate 8; and reference numeral 9 indicates an N type diffusion layer formed on each of the P type diffusion layer 11 and N type diffusion layer 10. Also, reference numeral 4 represents a floating gate formed on the P type silicon substrate 8 via a thin oxide film 7. Reference numeral 6 denotes a control gate formed on this floating gate 4 via the oxide film; reference numeral 3 indicates a drain electrode; and reference numeral 5 represents a source electrode. In other words, the memory cell shown in FIG. 16 is constructed like a MOSFET but having instead the N-channel type double gate structure. Thus, the information is stored in this transistor, and is held in this transistor in accordance with effecting a change of the threshold voltage thereof.
It should be noted that a transistor (referred to as a xe2x80x9cstorage transistorxe2x80x9d) of a memory cell, for storing information, discussed herein is of an N-channel storage transistor unless stated otherwise in the following description.
The information writing operation with respect to the memory cell represented in FIG. 16 is similar to that of EPROM. In other words, the writing operation of EEPROM shown in FIG. 16 is performed by injecting into the floating gate 4 a hot carrier produced adjacent to the drain region 9 connected to the drain electrode 3. The threshold voltage of the storage transistor with respect to the control gate 6 is higher than that of another storage transistor which does not perform the writing operation, while such a writing operation is carried out. In the erasing operation, on the other hand, the control gate 6 is grounded, and the high voltage is applied to the source electrode 5, whereby the high electric field is produced between the floating gate 4 and the source region 9 connected to the source electrode 5. Then, while utilizing the tunneling phenomenon via the thin oxide film 7, the electron which has been stored in the floating gate 4 is drawn via the source region 9 to the source electrode. As a result, the stored information disappears. In other words, the threshold voltage of the storage transistor is lowered with respect to the control gate 6. During the reading operation, in order to prevent a weak writing operation from being undesirably effected to the above-described memory cell, that is, to prevent undesired carriers from being injected into the floating gate, the voltages applied to both the drain electrode 3 and control gate 6 are limited to a relatively lower value. A lower voltage of, for instance, on the order of 5 volts is applied to the control gate 6. A magnitude of a channel current flowing through the storage transistor is detected in accordance with such applied voltages so as to determine whether or not the information stored in the memory cell corresponds to xe2x80x9c0xe2x80x9d or xe2x80x9c1.xe2x80x9d
In general, during the electrical erasing operation, when the erasing operation is continued for a long time, the threshold voltage of the storage transistor will become different from that of the storage transistor under the thermal balance, namely it may become a negative value. To the contrary, in case of EPROM where the stored information is erased by way of ultraviolet radiation, the threshold voltage of the storage transistor which is varied in accordance with the erasing operation is substantially equal to the threshold voltage which is obtained when this memory-device is manufactured. In other words, the threshold voltage of the storage transistor after the erasing operation may be controlled by the manufacturing conditions and the like of this memory device. However, as previously described, in the case that the stored information is electrically erased, the stored information disappears when the electron stored in the floating gate is drawn to the source electrode. As a consequence, if the erasing operation in connection with such an EEPROM as in FIG. 16 is continued for a relatively long time, a large quantity of electrons are drawn away from the floating gate into the source electrode via the source region as compared with a quantity of electrons which have been injected into the floating gate while the writing operation is carried out. Therefore, when the electrical disappearance or erasings of the stored information is continued for a relatively long time, the threshold voltage of the storage transistor attains a different value from the threshold voltage obtained when the memory device is manufactured. That is to say, when the erasing operation is performed, the threshold voltage of the storage transistor would no longer be equal to the threshold voltage determined by the manufacturing conditions thereof, in contrast to the EPROM.
The Applicants, in accordance with their investigative and research efforts, have measured the variations in the threshold voltage of the storage transistor caused by the electrical erasing operation. In FIG. 8, there is shown a relationship, based on such measured variations, between the threshold voltage of the storage transistor as varied by the length of the erasing operation. In the graphic representation shown in FIG. 8, the abscissa denotes the erase time, whereas the ordinate indicates the threshold voltage of the storage transistor. xe2x80x9cVoxe2x80x9d indicates that the threshold voltage is substantially equal to zero, xe2x80x9c+Vthsxe2x80x9d represents that the threshold voltage is equal to a positive voltage; and xe2x80x9cxe2x88x92Vthsxe2x80x9d indicates that the threshold voltage is equal to a negative voltage. Also, xe2x80x9cVthvxe2x80x9d represents a fluctuation in the threshold voltage after the erasing operation, which is caused by fluctuations and the like of the manufacturing conditions. From this figure, it should be understood that if the erasing operation is continued for a relatively long time, the threshold voltage with respect to an N-channel storage transistor, for example, is changed wherein it becomes a negative voltage. Similarly, it should be understood from this figure that different threshold voltage variations of the respective storage transistors may result by the erasing operation because of fluctuations in the manufacturing conditions. In addition, it should be understood from this figure that the fluctuations in the threshold voltage become large in accordance with the erasing time. That is to say, a difference in the threshold voltages of two storage transistors is enhanced or magnified in accordance with an increase in the erase time.
As previously described, when the threshold value of the storage transistor becomes negative, the readout operation becomes adversely influenced. This adverse influence will now be described with reference to FIG. 17. It is now assumed that the information stored is read from the memory cell 12 under the write condition. Reference numeral 17 shown in FIG. 17 indicates a sense amplifier. To bring the memory cell 12 into the selective condition, the selective voltage during the readout operation, for instance the power source voltage Vcc (5V) is applied to the word line 13 connected to the memory cell 12. During this time, the non-selection voltage (for example the ground voltage OV) during the readout operation is supplied to the word lines 15 etc. in order to bring the other memory cells 14 etc. into the non-selective condition. If the memory cell 14, which is connected to the data line 16 as is the memory cell 12 from which the stored information is to be read out, is in the non-selective condition and has developed a negative threshold voltage, even if the voltage of the word line 15, namely the voltage of the control gate of the memory cell becomes zero, since the undesired current (non-selective leak current) flows through the data line 16 via the memory cell 14 which has been brought into the non-selective condition, a delay in a readout time may occur and thus an erroneous reading operation may be induced.
Similarly, there is an adverse influence with respect to a writing operation if the storage transistor within the memory cell has developed a negative threshold voltage. Normally, in the case where the writing operation is performed by utilizing hot carrier transfer, the high voltage (Vpp) employed for the writing operation, which is externally applied, is applied via a switching MOSFET to the drain region of the storage transistor within the memory cell. The voltage drop in the above-described MOSFET is changed, depending upon the current flowing therethrough. As a consequence, under such a condition that the threshold voltage of the storage transistor becomes negative, the above-described voltage drop across the MOSFET becomes too large so that the voltage applied to the drain of the storage transistor within the memory cell is lowered by the above-described voltage drop. As a result, the time required for the writing operation may be increased.
Consequently, in the above-described EEPROM, a precise control must be implemented in order to control the value of the threshold value after the erasing operation.
In order to effect the electrical erasing operation of the stored information in a conventional EEPROM, for instance, as described on pages 152 to 153 in IEEE International Solid-State Circuit Conference in 1980, the EEPROM therein is constructed of storage transistors and selective transistors for blocking the non-selective leak current. Also, in this EEPROM, the program line is coupled to the control gate of the storage transistor thereof, whereas the selective line is coupled to the gate of the selective transistor. That is to say, both the storage transistor and selective transistor of each memory cell thereof are coupled to independent lines, respectively.
In FIG. 18, there is shown a sectional view of the memory cell of the electrical batch erasing type EEPROM which has been described on pages 76 to 77 in IEEE International Solid-State Circuit Conference in 1987. Although the operation of this memory cell is substantially the same as that of the memory cell shown in FIG. 16, the erasing operation of the stored information is different from that of the memory cell shown in FIG. 16. That is to say, the erasing operation of this EEPROM is carried out by utilizing the tunneling phenomenon effected between the floating gate and drain region. In this memory cell, though there is only one gate electrode to be connected to the word line, substantially two transistors are used to construct the memory cell. In other words, it can be assumed that the memory cell is arranged by the selective transistor and storage transistor in which both the gate electrode and control gate electrode are formed on a body. As previously described, since this memory cell essentially includes the selective transistor, the conventional problem of the nonselective leak current occurring during the readout time has been solved. However, since the writing operation is performed by the hot carrier required for a larger quantity of current, as compared with the writing operation effected by utilizing the tunneling phenomenon, the problem of the above-described adverse influence while the writing operation is executed is still present.
In the conventional EEPROM as described, for instance, on pages 152 to 153 in IEEE International Solid-State Circuit Conference in 1980, a single memory cell is constructed of a storage transistor and a selective transistor which are connected to respectively different word lines. However, in the memory cell of another type of EEPROM, such as of the electrically batch erasing type EEPROM as represented in FIGS. 16 and 18, it is constructed of a single storage transistor connected to a single word line. Such a specific arrangement as may be apparent in connection with the memory cells and the like shown in FIGS. 16 and 18 are herein represented by circuit diagrams. To this end, the representative circuit diagrams of the above-described memory cell are illustrated in FIGS. 19A and 19B. FIG. 19B shows a circuit diagram of the memory cell which has been announced at the IEEE International Solid-State Circuit Conference held in 1980. In the memory cell shown in FIG. 19B, symbols xe2x80x9cW1xe2x80x9d and xe2x80x9cW2xe2x80x9d denote different word lines, and symbol xe2x80x9cDxe2x80x9d represents a data line. Also, symbol xe2x80x9cQ1xe2x80x9d indicates a selective transistor whereas symbol xe2x80x9cQmxe2x80x9d represents a storage transistor. FIG. 19A shows a circuit diagram of the memory cell shown in FIGS. 16 and 18. As is apparent from this circuit diagram, a single memory cell is so constructed that a control gate of a single storage transistor Qm is connected to a single word line, a drain thereof is connected to a single data line xe2x80x9cD,xe2x80x9d and a source thereof is connected to a single source line xe2x80x9cS.xe2x80x9d While the reading/writing operations are performed, to select a desired single memory cell from a plurality of memory cells of the type according to FIG. 19A, only a single word line and a single data line are required to be selected. This cell which is selected, of course, corresponds to the selected word line xe2x80x9cWxe2x80x9d and to the selected data line xe2x80x9cD.xe2x80x9d In other words, a single memory cell can be defined by one word line and one data line. It should be noted that in FIG. 19A, the source line xe2x80x9cSxe2x80x9d is commonly used as the source lines xe2x80x9cSxe2x80x9d of all of the remaining storage transistors formed on the chip. Alternatively, each source line xe2x80x9cSxe2x80x9d provided can be commonly used with respect to a predetermined number of memory cells constituting a single memory block.
Since the memory cell shown in FIG. 19A can be arranged by a single storage transistor, the area on the chip required for forming the memory cell can be reduced to a small area substantially equal to that of EPROM. However, in order to realize the electrically batch erasing operation of the stored information, as described above, it is absolutely necessary to be capable of controlling the threshold voltage of the storage transistor after the erasing operation.
To this end, according to prior efforts, the erasing operation is subdivided into a certain number of erasing operations. Then, a confirmation determination is made as to whether or not the erasing operation is sufficient. If the erasing operation performed is determined to be insufficient or inadequate, the erasing operation is again repeated. In accordance with the above-described IEEE, J. Solid-State Circuits vol. 23 (1988), pages 1157 to 1163, there is proposed an algorithm relating to a control of the threshold voltage after such an erasing operation. In accordance with this publication, this algorithm is executed by the microprocessor which is provided separately with the electrically batch erasing type EEPROM. Also, in order to maintain the lower limit voltage xe2x80x9cVcc minxe2x80x9d of the operable power source during the normal read out operation, a description given therein requires that the verify voltage be generated in the chip of the EEPROM while implementing the above-described algorithm (erasing verify operation).
In the above-described prior art, since such an algorithm is performed by the microprocessor, a cumbersome operation is required to perform the erasing operation of the stored information while the electrically batch erasing type EEPROM is actually packaged within the system. Furthermore, since a relatively long time is required for erasing the stored information, the microprocessor is necessarily being occupied for the erasing operation of the above-described EEPROM. This causes a serious problem in that the overall system employed must actually be stopped, i.e. be unnecessarily halted.
As the flash EEPROM, a typical memory device is disclosed, for example, in Japanese Patent Application Laid-Open Publication No. 62(1988)-276,878.
The memory cell of the flash EEPROM will be herein called a FAST (Floating Gate Asymmetric Source and Drain Tunnel Oxide) type.
The FAST type memory cell has a construction of a floating gate type field-effect transistor similar to the FAMOS type of EPROM. One bit (one memory cell) can be constituted by one element, and excellent integration is therefore provided.
Writing is effected by injecting into a floating gate electrode a hot electron generated in the vicinity of a drain junction similar to FAMOS. A threshold voltage as viewed from a control gate electrode of the memory cell is increased by writing.
On the other hand, erasure is effected by grounding a control gate electrode, applying a positive high voltage to a source to thereby generate a high electric field between a floating gate electrode and the source, and drawing electrons accumulated on the floating gate electrode into the source utilizing a tunnel phenomenon through a thin gate oxide film. A threshold voltage as viewed from the control gate electrode is lowered by the erasure. Since the memory cell has not selective transistor, presence of negative threshold voltage (over-erasure state) is fatally defective.
Reading is effected by applying a low voltage of the order of 1 V to a drain, applying a voltage of the order of 5 V to a control gate electrode, and utilizing the fact that magnitude of a channel current floating at that time corresponds to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of information. The drain voltage is stepped down to prevent a parasitic weak writing operation.
Since in the aforementioned FAST type memory cell, writing and erasure are effected on the drain side and on the source side, respectively, it is desired that junction profiles are individually optimized so as to suit to respective operations. The above-described prior art has a source/drain asymmetric construction, in which in the drain junction, an electric field concentrated type profile for improving the writing efficiency is used whereas in the source junction, an electric field relaxation type profile capable of applying a high voltage is employed.
In a memory cell for effecting erasure drawing an electron from a floating gate electrode in a tunnel, how to minimize an electrostatic capacity coupling between a region (a source region in this instance) to which an erasure voltage is applied and a floating gate electrode is important in order to case the fineness of cell to be consistent with the lower voltage of erasure operation. In the FAST type memory cell, a superposed region of a floating gate electrode and a source for determining a capacity coupling is formed in a self-matching manner by diffusion of the source to reduce the value thereof.
Chip collective erasure type memories other than the above-described are as follows.
First, V. N. Kynett et al. disclose, in IEEE Int. Solid-State Circuits Conference, Digest of Technical Papers, pp. 140-141, Fe., 1989, a 1 Mb flash EEPROM of the chip collective erasure type which uses a memory cell based on the principle similar to the aforementioned FAST type. A memory cell area is 15.2 xcexcm2 (design rule; 1.0 xcexcm), and a working voltage for writing and erasure is 12 V. The low voltage operation is realized in the fine cell. However, this apparatus requires to external power sources, Vcc (5 V) and Vpp (12 V) for writing. This is because of the fact that a consumption current during rewriting operation is so high that a step-up power source of on-chip cannot be utilized.
Furthermore, S. D""Arrigo et al. disclose, in IEEE Int. Solid-State Circuits Conference, Digest of Technical Papers, pp. 132-133, February, 1989, a 256 kbit flash EEPROM of the chip collective erasure type. That is, (1) the tunnel phenomenon of electrons is utilized for writing as well as erasure, and (2) a region in which the gate oxide film used in the tunnel is thin is limited to a drain high concentration diffusion layer whereby a consumption current for rewriting operation may be reduced. A further feature of this memory is to apply a negative voltage to a control gate electrode in the erasure operation. Thereby, the voltage applied to the drain diffusion layer is stepped down to 5 V or so to increase an allowance with respect to junction pressure. However, in this apparatus, the tunnel region is not self-matched. Further, a selective transistor called a pass gate is contained in the cell, and therefore, this apparatus is inferior to the FAST type in terms of the fineness of cell and the low voltage operation.
Applicants have found that problems noted below involved in connection with the emission of electrons in the memory cell of EEPROM of the FLOTOX type as described above.
That is, one problem is that since a high voltage is applied to a drain electrode during emission of electrons from a floating gate, a high voltage is applied to an n+ diffusion layer forming a drain region and an n+/p junction portion to degrade the memory cell of the EEPROM.
Because of this, a high pressure-withstanding construction has been heretofore employed for the memory cell of the EEPROM. This poses a further problem in that the high pressure-withstanding construction of the memory cell of the EEPROM impairs the fineness thereof, to increase an area of a semiconductor chip used by the memory cell.
Although the FAST type memory cell as described above is a promising element having various advantages, it has problems as noted below.
A first problem is that a parasitic leak current flows from a source to a semiconductor substrate during erasure operation. This is a leak current peculiar to the FAST type memory cell resulting from the fact that a gate oxide film is thinned over the whole surface of the floating gate electrode. That is, when a high electric field (of the order of 10 MV/cm) necessary for the erasure operation is applied to the gate oxide film, paired electrons and holes caused by the tunnel between bands occur in the source region surface therebelow. Since the holes cannot prevent the outflow toward the substrate, a high leak current flows. It is noted that in the above-described FLOTOX type memory cell, the gate oxide film is thickened at the end of the high concentration diffusion layer, and therefore, the holes will not flow toward the substrate and no leak current occurs.
The presence of the leak current as described above causes a consumption current for the chip collective erasure operation to increase. Therefore, an external power source for erasure operation, other than a Vcc power source (normally, 5 V power source) for reading operation, supplied externally of the chip, is required.
A second problem is that when rewriting is repeated, durability with respect to the program disturb is materially degraded, making it difficult to secure reliability of array operation. The program disturb termed herein is the phenomenon wherein a threshold voltage of the memory cell varies in a word line semi-selective state where a writing high voltage is applied to a control gate alone of the memory cell.
G. Verma et al. reports, in IEEE 1988 Int. Reliability Physics Symposium, pp. 158-166, the degrading phenomenon of durability of the aforesaid program disturb. According to this report, the degradation of the program disturb durability results from the fact that a positive captured charge is formed in the gate oxide film by the erasure operation to accelerate the tunnel injection of electrons, which brings a cause of the program disturb. The formation of the positive captured charge is considered to be resulted from the fact that a hole generated in the tunnel between bands during the erasure operation is formed into a hot hole by obtaining energy from a high electric field between the source and the substrate, and it is injected into and captured by the gate oxide film in an extremely fine amount.
The aforementioned degradation phenomenon of the program disturb durability constitutes a severer restriction in the case where a memory array is divided into some blocks in a direction perpendicular to a word line, and rewriting operation is effected every block. In the case where the division of blocks is not taken into consideration, time for the memory cell exposed to the program disturb may be time of the sum for applying writing one by one to other memory cells on one and the same word line. On the other hand, considering the division of blocks, in the case where writing is applied to a certain block and thereafter rewriting of other blocks is repeated, the time becomes extended by approximately the times of rewriting.
A third problem is that the erasure operation by bit line unit is impossible to carry out in principle. The FAST type memory cell is a 1-element type memory cell which has no switch MOS. Therefore, when an erasure high voltage is applied to a source line, all the memory cells connected to the source line are simultaneously erased. Even if the source line is decoded, the block erasure by source line unit is merely enabled.
FIG. 52 schematically shows a sectional construction of the above-described FAST type memory cell. As previously mentioned, this memory element has a construction of a floating gate type electric field-effect transistor of 1-element/bit similar to the FAMOS type memory element of EPROM, which is excellent in high integration.
As previously mentioned, writing is carried out by injecting a hot carrier generated in the vicinity of a drain 1xe2x80x2 junction into a floating gate 2xe2x80x2 similar to EPROM. A threshold value as viewed from a control gate 4xe2x80x2 of a memory cell is increased by writing. On the other hand, erasure is carried out by grounding the control gate 4xe2x80x2, applying a high voltage to a source 3xe2x80x2 to thereby generate a high electric field between the floating gate 2xe2x80x2 and the source 3xe2x80x2, and drawing electrons accumulated on the floating gate 2xe2x80x2 into the source 3xe2x80x2 utilizing the tunnel phenomenon through a thin oxide film 5xe2x80x2. A threshold value as viewed from the control gate 4xe2x80x2 is lowered by the erasure. Reading is effected by applying a low voltage of the order of 1 V so that weak writing is hard to occur in the drain 1xe2x80x2, applying a voltage of the order of 5 V to the control gate 4xe2x80x2, and corresponding the magnitude of a floating channel current to 0 and 1 of information. In the figure, reference numeral 6xe2x80x2 designates a p-type silicon substrate; 7xe2x80x2 an n-type diffusion layer; 8xe2x80x2 an n-type diffusion layer of low concentration; and 9xe2x80x2 a p-type diffusion layer.
Furthermore, as previously mentioned, in the memory element in which the erasure operation is carried out by the tunnel of electron, how to minimize an electrostatic capacity coupling between a region to which erasure voltage is applied (a source region in this instance) and a floating gate electrode comprises a point to cause the fineness of cell to be consistent with the lower voltage of erasure. In the FAST type memory element, a gate oxide film below a floating gate electrode is wholly thinned (into a tunnel oxide film), and a superposed portion of the floating gate electrode and a source region is formed in a self-matching manner by diffusion of said region or the like to decrease the tunnel region of electrons to the limit and reduce the capacity coupling.
In the flash EEPROM using the above-described conventional FAST type memory element, security of controllability of a xe2x80x9c1xe2x80x9d state threshold voltage (a threshold voltage low level) realized by the electric collective erasure operation constitutes an important task. This is because of the fact that inferiority results from the following reading operation even if the threshold voltage after erasure is too high or too low.
In the case where the threshold voltage after erasure is to high, a current required to read xe2x80x9c1xe2x80x9d is short, resulting in an occurrence of degradation of the lower limit value of the read-out power source voltage or the read-out speed. That is, naturally, the erasure operation should not be insufficient.
On the other hand, when the threshold voltage after erasure is low to assume a depleted state, a current flows even into a memory element in which a word line is not selected during reading. Therefore, the xe2x80x9c0xe2x80x9d state where current does not flow originally is impossible to read. Since the FAST type memory element has no selective transistor, it cannot carry out even over-erasure.
As a result, in the flash EEPROM using the FAST type memory element, for applying an erasure voltage to a common source line to simultaneously and collectively erase a number of memory elements, it is required that no unevenness in erasure characteristic of individual memory elements exists or at least such unevenness is restrained to a minimum.
However, actually, when the collective erasure operation is effected in an LSI level, a large unevenness appears between erasure characteristics, due to the influence of various factors such as unevenness of element construction, unevenness of characteristic of the tunnel oxide film, and the like. How to manage this poses a great problem in design.
A first object of the present invention is to provide a nonvolatile semiconductor memory device of high reliability.
A second object of the present invention is to provide a small-sized nonvolatile semiconductor memory system.
A third object of the present invention is to provide a nonvolatile semiconductor memory device using the aforementioned FAST type memory cell which eliminates the necessity of an external power source exclusively used for erasure operation.
A fourth object of the present invention is to provide a nonvolatile semiconductor memory device using the aforementioned FAST type memory cell, which is hard to be affected by a program disturb and can realize electric erasure per block unit.
A fifth object of the present invention is to provide a nonvolatile semiconductor memory device using the aforementioned FAST type memory cell, which can perform erasure operation per bit unit.
A sixth object of the present invention is to provide a nonvolatile semiconductor memory device using the aforementioned FAST type memory cell, which can perform erasure operation using a single power source (for example, 5V power source) which is used for reading operation and writing operation.
A seventh object of the present invention is to provide a nonvolatile semiconductor memory device using the aforementioned FAST type memory element, in which even if significant unevenness between erasure characteristics of a memory element for carrying out collective erasure operation is present, unevenness of a threshold voltage after erasure can be minimized.
An eighth object of the present invention is to provide a semiconductor nonvolatile memory device capable of essentially performing an electrical erasing operation without lowering the throughput capability of an entire system while actually packaging the semiconductor nonvolatile memory device to the system.
A ninth object of the present invention is to provide an information processing system capable of essentially realizing, i.e., fully implementing, an electrical erasing operation without lowering the throughput capability of the entire system, with EEPROMs packaged with the system.
A tenth object of the present invention is to provide an electrically batch erasing type EEPROM capable of automatically performing an erasing operation, to which an erasing instruction is merely supplied.
The above-described objects and other objects, and also novel features of the present invention will become apparent from the following descriptions and accompanying drawings.
Typical embodiments according to the present invention disclosed, which will be described in greater detail subsequently, will now be simply summarized as follows. That is, with respect to an electrically batch erasing type EEPROM including a memory array in which electrically erasable storage transistors (nonvolatile storage elements) are arranged in a matrix form, an erasing operation is performed in response to an externally supplied erasing instruction. Thereafter, a reading operation is carried out at least one time for the nonvolatile memory elements to which the erasing operation has been executed. Further, an erasing control circuit for controlling a continuation and interruption of the erasing operation in response to the readout information, is built in an EEPROM. Also, an EEPROM having the above-described erasing function is actually packaged with an information processing system including a microprocessor, and an erasing operation is automatically performed by the internal erasing control circuit, which is separated from the microprocessor, in accordance with the erasing instruction derived from the microprocessor.
In accordance with the above-described means, since an EEPROM per se according to the present invention owns the automatic erasing function which includes a reading operation for providing a confirmation as to whether or not the stored information has been erased, during the erasing operation while actually packaging the EEPROM to the system, a time required for controlling the operation of an EEPROM from the microprocessor is equal to a very short period of time from the time the erasing operation is commenced. This causes the load on the microprocessor to be considerably reduced.
A nonvolatile semiconductor memory device provided with an electrically erasable type nonvolatile memory cell composed of a MOSFET having a two-layer gate construction comprising a floating gate and a control gate is provided with a negative voltage generation circuit for applying a negative voltage to the control gate of said MOSFET and a low voltage generation circuit for applying a low voltage to a drain electrode of said MOSFET. Thereby, the aforementioned first and second objects can be achieved. That is, an emission of electrons from the floating gate, a potential of the voltage applied to the control gate is lower than a conventional GND potential. Accordingly, even if a potential of the voltage applied to the drain electrode is lower than the conventional potential through a potential of the voltage applied to the control gate, a potential difference required for emission of electrons can be secured between the floating gate and the drain electrode. That is, in emission of electrons from the floating gate, the voltage applied to the drain electrode can be stepped down as compared with that of prior devices. It is therefore possible to prevent degradation of the memory cell of the EEPROM.
Furthermore, the voltage applied to the drain electrode is stepped down as compared with that of prior devices, whereby the memory cell of the EEPROM is not necessary to have a high pressure withstanding construction. It is therefore possible to decrease the size of the memory cell and to miniaturize the nonvolatile semiconductor memory device.
For achieving the third and sixth objects, it is designed so that in carrying out the collective erasure operation by the nonvolatile semiconductor memory device using the FAST type memory cell, a voltage applied to a source region (or a drain region) of each memory cell is supplied from a Vcc power source (A power source supplied externally of the chip and normally used for reading operation; this is applied thereafter) of the nonvolatile semiconductor memory device, an erasure voltage reversed in polarity to that of the Vcc power source is applied to a control gate electrode of each memory cell, and said erasure voltage is supplied from a voltage conversion circuit (a step-up circuit) within the nonvolatile semiconductor memory device. The value of the erasure voltage having a reversed polarity is determined according to the constructional constant and characteristics of the memory cell, for example, the value of the order of Vccxe2x88x922 Vcc.
Next, the fourth object is realized by using the means for achieving the above-described third and sixth objects and by dividing the block in a direction of a word line so that memory cells connected to the same word line belong to the same block.
The fifth object is realized, in the means for achieving the above-described third and sixth objects, by an arrangement wherein a source line (or a data line) for applying an erasure voltage and a word line are decoded, and erasure operation is effected merely by a memory cell which is present at an intersection between a pair of selected source line (or a data line) and a word line.
Circuits for a typical example of operation of a memory array corresponding to the means used to achieve the third to sixth objects and working voltages of various parts are shown in FIGS. 29 to 31.
In this example, a memory array M-ARRAY comprises FAST type memory cells (n channel) M1xe2x80x2 to M9xe2x80x2 arranged in three lines and three rows, and operation thereof takes place through word lines W1xe2x80x2-W3xe2x80x2, data lines D1xe2x80x2-D3xe2x80x2, and a common source line CSxe2x80x2.
FIG. 29 shows the collective erasure operation with the whole memory array M-ARRAY as a single unit.
In this case, a negative erasure voltage (xe2x88x927V) is applied to all word lines W1xe2x80x2 to W3xe2x80x2, and a positive erasure voltage (+5) is applied to the common source line CSxe2x80x2. +5V of the common source line CSxe2x80x2 is supplied from the Vcc power source externally of the device, and xe2x88x927V of the word line is supplied from the voltage conversion circuit within the device. At that time, the substrate and the data line have a ground potential. It is noted that writing and reading operations are carried out by decoding the data line and the word line and selecting the memory cell at the intersection, similar to the conventional chip collective erasure type flash EEPROM of the two-power source system.
Next, FIG. 30 shows the case where a group of memory cells MB1xe2x80x2, MB2xe2x80x2 and MB3xe2x80x2 connected to the word lines as surrounded by the broken lines in the figure are handled as a bunch of memory blocks to effect the erasure operation. That is, the group of memory cells connected to the same word line are selectively erased.
In this case, the word line to which is applied the negative erasure voltage (xe2x88x927) is decoded to thereby select a memory block for effecting erasure. Other configurations are similar to those shown in FIG. 29.
Next, FIG. 31 shows the case where a suitable I bit in the memory array M-ARRAY is selected to effect erasure operation.
In this case, the word line to which is applied the negative erasure voltage (xe2x88x927V) is decoded, and the positive erasure voltage (5V) is applied from the data line. The data line is decoded whereby erasure is effected by the memory cell at an intersection between the selected word line and data line. At that time, the substrate and the common source line are at a ground potential.
Writing is carried out by applying a writing voltage to the common source line and the selected word line and grounding the selected data line. At the memory cell located at the intersection, injection of a hot electron occurs from the source region side to realize the writing operation. At that time, non-selected data lines are separated one by one to provide an open state, and the non-selected word lines are at a ground potential. Reading operation is carried out by decoding the data line and the word line to select a memory cell at an intersection, similar to the conventional chip collective erasure type flash EEPROM of the two-power source system.
The intended objects are realized by the aforementioned means.
First, the Vcc power source is applied to a source region or a drain region of each memory cell, an erasure voltage having a polarity reversed to that of the Vcc power source is applied to a control gate electrode, and said erasure voltage is supplied from a voltage conversion circuit provided within the memory device. Function of such a construction as just mentioned is as follows.
In carrying out the collective erasure operation by the nonvolatile semiconductor memory device using the FAST type memory cell, the source region through which flows a large leak current (for example, several 10 mA with 1 Mbit) is directly driven by the Vcc power source. It is necessary for preventing the lowering of erasure speed to apply an erasure voltage reversed in polarity to that of the Vcc power source to the control gate electrode. However, since only a fine tunnel current (for example, current of the order of 10 xcexcA with 1 Mb) directly contributed to the erasure flows into the control gate electrode, it can be driven by the voltage conversion circuit (step-up circuit) provided within the nonvolatile semiconductor memory device. In this manner, the chip collective erasure operation by the Vcc single power source can be realized without sacrifice of the erasure speed.
Next, the function of the arrangement wherein the block is divided in a direction of the word line so that the memory cell connected to the same word line belongs to the same block, in addition to the aforementioned arrangement, is as follows.
Since the erasure voltage applied to the source region of the memory cell is stepped down from the conventional Vpp voltage (for example, of the order of 12V) to the Vcc voltage (for example, of the order of 5V), it is possible to materially restrain the phenomenon in which, as shown in FIG. 32, a hole generated in a tunnel between bands is formed into a hot hole by an electric field between the source and the substrate, which is then injected into and captured by the gate oxide film. Since the memory cells connected to the same word line are collectively rewritten without fail, the program disturb time experienced by the individual cells may be of the sum of times required for writing other memory cells on the same word line. It is possible to avoid the phenomenon in which the disturb time increases depending on times of rewriting. With this, the nonvolatile semiconductor memory device which is excellent in the program disturb durability and can provide electric erasure per block unit is realized.
Next, in the arrangement wherein the source line (or the data line) to which is applied the erasure voltage and the word line are decoded and the erasure operation is effected merely by the memory cell located at the intersection between the pair of selected source line (or data line) and word line, the source lines (or data lines) to which erasure voltage different in polarity from each other are applied and the word lines are decoded whereby the erasure operation can be selectively carried out by the memory cell located at the intersection. At that time, the tunnel phenomenon of electrons which controls erasure greatly depends upon the intensity of the electric field of the oxide film, and therefore, substantial erasure can be avoided from occurrence at the semi-selected memory cell in which only either data line or word line is selected.
The aforementioned seventh object is realized by individually controlling substantial terminals of the collective erasure operation every memory element or every bunch of some memory elements according to individual erasure speeds of the memory elements. Specifically, this can be realized by a combination of means described below as shown in FIG. 50.
First, a memory array M-ARRAY is divided into two blocks or more (in FIG. 50, MB1xe2x80x2 to MB4xe2x80x2), each block comprising at least one memory element. Means (in FIG. 50, ED1xe2x80x2-4xe2x80x2) for independently performing electric erasure every block are provided.
Second, there is provided means (in the figure, read-out device SAxe2x80x2) which determines, prior to the electric erasure, if erasure is not required since threshold voltages of all memory elements in the block are low, or even at least one element of high voltage is present.
Third, there is provided means for impeding an application of an erasure voltage so that the collective erasure operation is not carried out when erasure is not required because threshold voltages of all the memory elements within the block are low. That is, there is provided a function in the means ED1xe2x80x2-ED4xe2x80x2 to receive output of the SAxe2x80x2 to determine if an erasure voltage is applied.
Finally, when necessary and sufficient erasure operation was carried out with respect to all the memory elements, the collective erasure terminates. This determination may be made within the system or by means of an external control.
While in FIG. 50, the case has been shown in which the memory array M-ARRAY has one read-out device SAxe2x80x2, it is to be noted that generally, 8 sets or 16 sets of memory arrays and read-out devices SAxe2x80x2 are provided so that read/write per 8-bit unit or 16-bit unit may be carried out. In case of the 8 sets, an arrangement as shown in FIG. 51 is employed.
Furthermore, while in FIG. 50, it is assumed that the whole memory array M-ARRAY is erased, it is to be noted that a partial erasure for erasing only a part among them may be employed. That is, in simultaneously erasing blocks MB1xe2x80x2 and MB2xe2x80x2, the MB1xe2x80x2 and MB2xe2x80x2 form blocks to constitute the same.
Thereby, the collective erasure operation as the chip is continued until the latest erasure among all the memory elements terminates. However, paying attention to the individual erasing blocks, further substantial erasure will not be carried out with respect to memory elements which have been erased to a level as needed. As a result, even if unevenness in erasure characteristics of memory elements subjected to the collective erasure is present, it is possible to precisely arrange the threshold voltage after termination of erasure to the desired value.
The above and other objects and novel features of the present invention will become more apparent from the detailed description given in this specification together with the accompanying drawings of the preferred embodiments.